CPU |
SH7709AF133 (208P QFP) |
Clock |
128 MHz (16 MHz quarts crystal units are used.) |
Operation performance |
173 MIPS |
Memory |
Flash ROM 1Mbyte (16 bit width)
SDRAM 16Mbyte (32 bit width)
EPROM (Not packaged) 128K~1Mbyte(8 bit width)
SRAM 128 Kbyte (8 bit width)
Cache 16 Kbyte |
External memory chip
select |
Chip select terminal: 6, PCMCIA interface incorporated
CS0: Flash ROM, CS3: SRAM, CS4: SDRAM CS5:EPROM
used
Each memory is maskable.
CS0 and CS5 are interchangeable. (For debugging.) |
Memory back up |
For switching back-up.
SRAM back up can be achieved by connecting the back-up battery, etc.
to the outside. |
I/O |
Serial interface 3 CH
Parallel interface I/O 8 bit x 12 (Multiple use purpose terminal included.) |
Timer/Counter |
32 bit timer 3 channels |
Interruption |
Interruption controller incorporated
External 6 (Level interruption 16) NMI 1, other internal surrounding
interruption |
DMA |
DMA controller incorporated 4 channels |
DRAM |
SDRAM, DRAM controller incorporated |
RTC |
Internal clock, calendar function, 32.768 kHz crystal
connected. |
Reset |
Reset switch incorporated. External reset is possible.
(Open collector) |
Operation mode |
Can be switched by DIP-SW. |
External connection |
60 PIN connector x 2 (2.54 pitch)
50 PIN connector x 1 (2.54 pitch)
Connector for adapter for RS232
Power source connector |
Power source voltage |
5 V ± 10% (Internal I/O: 3.3 V CPU core: 1.9
V) |
Electrical consumption |
MAX 500 mA |
Substrate size |
120 x 90 (mm) 4 layer substrate |
Accessories |
Operation manual, circuit drawing, power cable, sample
program and downloader |